Modern microprocessors and system-on-a-chip (SoC) designs operate on multiple power supply levels. For example, input-output circuits (I/Os) generally operate at higher power supply levels than the core of the processor because I/Os may require higher voltage level swings to transfer data across long transmission lines. The core of the processor generally operates at a lower power supply level to save power dissipation where most of the circuits reside. Similarly, Phase Locked Loops (PLLs) require quite power supply levels that are shielded from the noise generated on the power supply levels from the core of the processor. In multi-core processors each core may operate on a different power supply domain resulting in a complex system of multiple power supply domains between cores and within cores.
For circuits on one power supply domain to communicate with a circuit on another power supply domain, interface circuits are used. These interface circuits are called level shifters. Typically, level shifters have asymmetric switching delays resulting in a different duty cycle at the output as compared to the input of the level shifter. This asymmetric switching delay results from two distinct paths for each rising and falling input signal transition.
FIG. 3A refers to one such level shifter 300 when used as a standalone level shifter. When an input signal A, which operates between power supply level Vcc1 and ground, switches from ground to Vcc1, the NMOS transistor 301 turns on and discharges node D# by overcoming the pull-up strength of PMOS transistors 303 and 302. Consequently, the PMOS transistors 304 and 305 pull up node D to power supply level Vcc2 because the NMOS transistor 307 is off due to signal A#. This causes the output node B to transition from ground to Vcc2 via inverter 308. When the input signal A transitions from Vcc1 to ground then the NMOS transistor 307 turns on and discharges node D by overcoming the PMOS transistors 304 and 305. Consequently, the PMOS transistor 303 and 302 pulls up node D# since node A is at ground. This causes the output node B to transition from Vcc2 to ground via the inverter 308. Since the level shifter has two distinct paths for each rising and falling transitions of the input signal A, the switching delays through the level shifter circuit become asymmetric.
For critical signals such as clock signals, asymmetrical switching, which is characteristic of a level shifter, can cause duty cycle variations in the clock signal resulting in timing contingencies. For example, an asymmetric clock signal from a typical level shifter may result in setup and hold time violations (min/max delays). These timing contingencies may reduce the overall operating frequency of the system.